1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an ESD protection circuit.
2. Description of the Related Art
Generally, an oscillator circuit used in electronic equipment or the like is formed on a semiconductor substrate and connected to the semiconductor substrate through a crystal oscillator disposed at another location and through an input/output terminal. In such a case, there is a fear in that a main circuit portion of the oscillator circuit is destroyed due to a surge voltage that invades the oscillator circuit from an external through the input/output terminal. Accordingly, in order to protect the main circuit portion of the oscillator circuit from the electrostatic discharge (ESD), an electrostatic protection circuit is disposed at the input/output terminal side.
FIG. 6 shows an example of the oscillator circuit. An oscillator circuit 10 includes an input terminal 1 and an output terminal 2 which are disposed on a semiconductor integrated circuit chip, an electrostatic protection circuit (hereinafter referred to as “ESD protection circuit”) 3, a CMOS inverter 4 having an input end that is high in impedance, a feedback resistor R1, an ESD protection circuit 5, a crystal oscillator 7, a capacitor C1, and a capacitor C2.
The ESD protection circuit 3 is disposed between the input terminal 1 and the input end of the CMOS inverter 4. The ESD protection circuit 3 includes: a p-channel MOS transistor P1 having a gate end and a source end connected to a high potential side power supply VDD, and a drain end connected to the input end of the CMOS inverter 4; and an n-channel MOS transistor N1 having a gate end and a source end connected to a low potential side power supply VSS, and a drain end connected to the input end of the CMOS inverter 4. Likewise, the ESD protection circuit 5 is disposed between the output terminal 2 and the output end of the CMOS inverter 4. The ESD protection circuit 5 includes: a p-channel MOS transistor P2 having a gate end and a source end connected to the high potential side power supply VDD, and a drain end connected to an output end of the CMOS inverter 4; and an n-channel MOS transistor N2 having a gate end and a source end connected to the low potential side power supply VSS, and a drain end connected to the output end of the CMOS inverter 4.
In this case, the crystal oscillator 7 is disposed in the external portion of the semiconductor integrated circuit chip, and connected between the input terminal 1 and the output terminal 2. Also, the capacitor C1 is connected between the input terminal 1 and the low potential side power supply VSS, and the capacitor C2 is connected between the output terminal 2 and the low potential side power supply VSS. Further, the input end of the CMOS inverter 4 is connected to the input terminal 1, and the output end of the CMOS inverter 4 is connected to the output terminal 2. Also, the feedback resistor R1 is connected between the input end and the output end of the CMOS inverter 4.
With the above-mentioned configuration, an oscillation signal obtained from the output end of the CMOS inverter 4 is given to another circuit (not shown) as a clock signal.
In this case, with the connection of the feedback resistor R1 to the CMOS inverter 4, the CMOS inverter 4 functions as an inverter amplifier. FIG. 7 is a diagram showing an input/output characteristic of the inverter amplifier. An operating point bias voltage at the input end of the CMOS inverter 4 is stable at a point (point A) of a threshold voltage of the CMOS inverter 4 where the gain (output voltage variation/input voltage variation) as the inverter amplifier becomes maximum, and an oscillation starts at a resonant frequency of the crystal oscillator 7 by the gain of the inverter amplifier and the phase adjustment due to the capacitor C1 and the capacitor C2.
However, when the supply voltage drops along with manufacturing process becoming finer, a threshold voltage of the MOS transistor is also decreased. As a result, a leakage current occurs in a source-drain path of the MOS transistor that is normally off. Further, in the case where an ambient temperature increases, the leakage current exponentially increases with respect to an increase in the temperature. Also, the leakage currents of the n-channel MOS transistor and the p-channel transistor are not always equal to each other depending on the manufacturing process. In this case, there is a strong possibility that a problem is caused in the circuit operation depending on the circuit configuration of the above-mentioned oscillator circuit. For example, in the ESD protection circuit 3 of FIG. 6, in the case where the leakage current of the p-channel transistor P1 is larger than the leakage current of the n-channel MOS transistor N1 (for example, twice or more), the leakage current of the p-channel transistor P1 flows in the feedback resistor R1 side because an input impedance of the CMOS inverter 4 is extremely high. Accordingly, the operating point bias voltage at the input end of the CMOS inverter 4 is deviated by the voltage drop that is developed at both ends of the feed resistor R1, thereby deteriorating the duty ratio of a waveform that is output from the oscillator circuit. Further, because the leakage current exponentially increases with respect to an increase in temperature, the voltage fluctuates up to a point (point B of FIG. 7) at an end of a dynamic range as the inverter amplifier at the time of a high temperature, and the gain becomes 1 or lower to stop the oscillation. JP 2003-133855 A discloses a temperature compensation circuit having an output end that is connected to an input end of an input circuit so as to make a voltage at the input end of the input circuit equal to a reference voltage in order to suppress a variation in the operating point bias voltage due to the leakage current.